Nand or nor which is better

Asked 7 years, 6 months ago. Active 3 years ago. Viewed 75k times. According to my understanding delay would be the same.

Nick Alexeev Curious Curious 1 1 gold badge 3 3 silver badges 12 12 bronze badges. It appears that the OP is referring to the internal design of IC's, and not any preference for logic designers to use one or the other, which is what I was mistakenly referring to.

Add a comment. Active Oldest Votes. NAND offers less delay. NOR occupies more area. NAND uses transistors of similar sizes. When designing the layout mask, it would be easier if my transistors are of same dimension. I can make mask by 'copy pasting' or something like that. Time and effort and hence cost can be reduced. Correct me if its wrong. The way the Cmos Nand topology is, it lends itself to having more equal sizes of transistors as you can see from here: If either input is low, a single Pmos resistance drives the output high.

Let us discuss why it is so:. We know that when output is at logic 1, pull up structure for the output stage is on and it provides a path from VDD to output. Similarly, pull down structure provides a path from GND to output when output is logic 0. Pull up and pull down resistances are one of major factor in determining the speed of cell. Log in Register. Search only containers. Search titles only. Search Advanced search…. New posts.

Search forums. Log in. Install the app. Contact us. Close Menu. Welcome to EDAboard. To participate you need to register. Registration is free. Click here to register now. Register Log in.